Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
BLOCK_TRANSFER_INST |
46 |
12 |
0 |
12 |
25 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
ACTIVE_TRANSFER_INST_1 |
30 |
13 |
9 |
13 |
32 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
ACTIVE_TRIGGER_INST |
34 |
13 |
13 |
13 |
30 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
wireOR |
66 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
ACTIVE_TRANSFER_LIBRARY_INST |
26 |
1 |
0 |
1 |
27 |
1 |
1 |
1 |
8 |
0 |
0 |
0 |
0 |
SPI_IFACE_INST|read_spi_inst |
4 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
SPI_IFACE_INST|write_spi_inst |
11 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
SPI_IFACE_INST |
13 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |