Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
BLOCK_TRANSFER_INST |
46 |
12 |
0 |
12 |
25 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
ACTIVE_TRIGGER_INST |
34 |
13 |
13 |
13 |
30 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
wireOR |
44 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
ACTIVE_SERIAL_LIBRARY_INST|ENDPOINT_REGISTERS_INST |
36 |
0 |
0 |
0 |
35 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
ACTIVE_SERIAL_LIBRARY_INST|FT_245_STATE_MACHINE_INST |
23 |
1 |
0 |
1 |
23 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
ACTIVE_SERIAL_LIBRARY_INST|ACTIVE_TRANSFER_UART_INST|uart_inst|TX_INST |
12 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
ACTIVE_SERIAL_LIBRARY_INST|ACTIVE_TRANSFER_UART_INST|uart_inst|RX_INST |
5 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
ACTIVE_SERIAL_LIBRARY_INST|ACTIVE_TRANSFER_UART_INST|uart_inst |
14 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
ACTIVE_SERIAL_LIBRARY_INST|ACTIVE_TRANSFER_UART_INST |
6 |
0 |
1 |
0 |
3 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
ACTIVE_SERIAL_LIBRARY_INST |
25 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
SPI_IFACE_INST|read_spi_inst |
4 |
0 |
0 |
0 |
10 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
SPI_IFACE_INST|write_spi_inst |
11 |
0 |
0 |
0 |
3 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
SPI_IFACE_INST |
13 |
0 |
0 |
0 |
12 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |