| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| BLOCK_TRANSFER_INST |
46 |
12 |
0 |
12 |
25 |
12 |
12 |
12 |
0 |
0 |
0 |
0 |
0 |
| ACTIVE_TRANSFER_INST_4 |
30 |
13 |
9 |
13 |
31 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| ACTIVE_TRANSFER_INST_3 |
30 |
13 |
9 |
13 |
31 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| ACTIVE_TRANSFER_INST_2 |
38 |
13 |
9 |
13 |
31 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| ACTIVE_TRANSFER_INST_1 |
30 |
13 |
9 |
13 |
32 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| ACTIVE_TRIGGER_INST |
34 |
13 |
13 |
13 |
30 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| wireOR |
132 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ACTIVE_SERIAL_LIBRARY_INST|ENDPOINT_REGISTERS_INST |
36 |
2 |
0 |
2 |
47 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
| ACTIVE_SERIAL_LIBRARY_INST|FT_245_STATE_MACHINE_INST |
23 |
1 |
0 |
1 |
27 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
| ACTIVE_SERIAL_LIBRARY_INST|ACTIVE_TRANSFER_UART_INST|uart_inst|TX_INST |
12 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ACTIVE_SERIAL_LIBRARY_INST|ACTIVE_TRANSFER_UART_INST|uart_inst|RX_INST |
5 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ACTIVE_SERIAL_LIBRARY_INST|ACTIVE_TRANSFER_UART_INST|uart_inst |
14 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ACTIVE_SERIAL_LIBRARY_INST|ACTIVE_TRANSFER_UART_INST |
6 |
0 |
1 |
0 |
3 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
| ACTIVE_SERIAL_LIBRARY_INST |
25 |
0 |
0 |
0 |
25 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| SERIAL_CLOCK_INST |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| UC_CONTROLLER_INST |
54 |
0 |
22 |
0 |
53 |
0 |
0 |
0 |
24 |
0 |
0 |
0 |
0 |
| I2C_COMMS_INTERFACE_0_INST|I2C_PROTOCOL_LAYER_INST|I2C_TRANSMIT_FIFO|U_MEM_ARRAY |
17 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| I2C_COMMS_INTERFACE_0_INST|I2C_PROTOCOL_LAYER_INST|I2C_TRANSMIT_FIFO|U_READ_CTRL |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| I2C_COMMS_INTERFACE_0_INST|I2C_PROTOCOL_LAYER_INST|I2C_TRANSMIT_FIFO|U_WRITE_CTRL |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| I2C_COMMS_INTERFACE_0_INST|I2C_PROTOCOL_LAYER_INST|I2C_TRANSMIT_FIFO |
13 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| I2C_COMMS_INTERFACE_0_INST|I2C_PROTOCOL_LAYER_INST|I2C_RECEIVE_FIFO|U_MEM_ARRAY |
17 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| I2C_COMMS_INTERFACE_0_INST|I2C_PROTOCOL_LAYER_INST|I2C_RECEIVE_FIFO|U_READ_CTRL |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| I2C_COMMS_INTERFACE_0_INST|I2C_PROTOCOL_LAYER_INST|I2C_RECEIVE_FIFO|U_WRITE_CTRL |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| I2C_COMMS_INTERFACE_0_INST|I2C_PROTOCOL_LAYER_INST|I2C_RECEIVE_FIFO |
13 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| I2C_COMMS_INTERFACE_0_INST|I2C_PROTOCOL_LAYER_INST|I2C_ACK_INST |
6 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| I2C_COMMS_INTERFACE_0_INST|I2C_PROTOCOL_LAYER_INST|I2C_RECEIVE_INST |
4 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| I2C_COMMS_INTERFACE_0_INST|I2C_PROTOCOL_LAYER_INST|I2C_TRANSMIT_INST |
12 |
0 |
0 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| I2C_COMMS_INTERFACE_0_INST|I2C_PROTOCOL_LAYER_INST |
14 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
| I2C_COMMS_INTERFACE_0_INST |
13 |
0 |
4 |
0 |
7 |
0 |
0 |
0 |
17 |
0 |
0 |
0 |
0 |