| Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
| BLOCK_TRANSFER_INST |
46 |
4 |
0 |
4 |
41 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
| ACTIVE_TRANSFER_INST |
30 |
13 |
9 |
13 |
32 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| ACTIVE_TRIGGER_INST |
34 |
13 |
13 |
13 |
30 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
| wireOR |
66 |
0 |
0 |
0 |
22 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ACTIVE_TRANSFER_LIBRARY_INST |
26 |
1 |
0 |
1 |
27 |
1 |
1 |
1 |
8 |
0 |
0 |
0 |
0 |
| BLOCK_IN_FIFO|U_MEM_ARRAY |
17 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| BLOCK_IN_FIFO|U_READ_CTRL |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| BLOCK_IN_FIFO|U_WRITE_CTRL |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| BLOCK_IN_FIFO |
13 |
0 |
0 |
0 |
13 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| ACTIVE_CONTROL_REG_INST |
11 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_inst|TX_INST |
12 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_inst|RX_INST |
5 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
| uart_inst |
14 |
0 |
0 |
0 |
11 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |